The disclosures herein relate in general to electronic circuitry, and in particular to a method and system for comparing digital values.
In one example of asynchronously communicating a serial data stream from a transmitter to a receiver, the receiver implements a binary type of clock recovery technique, in which the receiver suitably adjusts a phase of its clock in response to phase differences between: (a) such clock; and (b) transitions in the data stream. In response to such clock having more “early” events than “late” events (within a particular number of consecutive bit times), the receiver delays the phase of such clock to make it less early. Conversely, in response to such clock having more “late” events than “early” events (within the particular number of consecutive bit times), the receiver advances the phase of such clock to make it less late.
To determine whether such clock has more “late” events than “early” events (within the particular number of consecutive bit times), some previous techniques have computed a total number of such “late” events, a total number of such “early” events, and a difference between those total numbers (including magnitude and sign of such difference). However, if the particular number of consecutive bit times is relatively large, then such techniques could impose a relatively large amount of combinational logic, which may be inefficient and cause the receiver to operate at lower frequency.